Energy-Efficiency Pipelined Architecture Design for RRAM-Based Digital Computing-in-Memory Applications

RRAM is a highly promising technology for implementing high-density in-memory computing, particularly suitable for edge AI applications. However, the efficiency and accuracy of conventional RRAM-based computing-in-memory (CIM) architectures are hindered by substantial accumulation currents and device variability. In this work, we present an enhanced RRAM-based CIM architecture that aims to balance accuracy, energy efficiency, and hardware area. By using the dynamic voltage sense amplifier (DVSA), the proposed approach can lower the read currents of low resistance state (LRS) cells, contributing to reduced overall power consumption while maintaining system efficiency. Additionally, the pipeline architecture streamlines data processing, reducing the number of DVSAs and effectively minimizing both area and power consumption with limited increasing in latency. Compared to previous RRAM-based designs, the proposed solution achieves a 11.4% and 36.8% reduction in area and power consumption, respectively with about 1.1× energy-efficiency improvement. Based on the significant contribution, the proposed approach is suitable for edge AI devices applications.