Repair and Timing-Aware Signal Path Assignment for Inter-Die Interconnects

Advanced 2.5/3D packaging technologies have dramatically increased the number of inter-die interconnects. However, with increasing inter-die interconnects, manufacturing yield becomes a concern and makes repair mandatory. This paper proposes a path assignment technique that constructs, for each inter-die signal, the normal and repair paths that meet the timing constraints. We model signal path assignment as an ILP problem and utilize bounding boxes for search space pruning. Furthermore, one can switch between total wire length and repairability optimization by properly setting the maximum repair chain length.