A Low-Cost QuadrupleNode-Upset Tolerant Latch Design and Recovery Rate Optimization Algorithm

With the continuous shrinking of nanoscale CMOS technology, the critical charge of circuit nodes has significantly decreased, rendering the nodes highly susceptible to soft errors. In this paper, a high-performance single-node-upset recovery memory cell (HSRM) is proposed. Based on four HSAMs, a latch namely QUAD-HSRM is introduced, which can completely tolerate quadruple-nodeupset (QNU). Additionally, a circuit matrix-based verification algorithm is proposed, which is not limited to C-element, and can automatically detect the multi-node-upset recovery rate and blocking rate of latches. Based on this algorithm, an optimization algorithm for automatically improving the recovery rate of latches was proposed, and using this algorithm, the QUAD-HSRM was optimized to obtain the QUAD-HSRM-PRO. Compared to the QUAD-HSRM, the QNU recovery rate of the QUAD-HSRM-PRO has increased from 54.94% to 95.76%. Compared to other QNU hardened latches (LC-QNUTL, QRHIL, LDAVPM, MURLAV), the QUAD-HSRM-PRO shows an average power reduction of 45.02%, an average PDP reduction of 33.07%, an average setup time reduction of 8.00%, an average Qcirt increase of 80.56%.