BayesBB: A 9.6-Gb/s 1.61-ms Configurable All-Message-Passing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO Systems

Cell-free massive multi-input multi-output (CF-mMIMO) has emerged as a promising alternative for the forthcoming beyond 5G and 6G (B5G/6G) systems. As an imperative part of supporting B5G/6G applications, baseband (BB) chips encounter more challenging key performance indicator (KPI) requirements. To achieve the B5G/6G goal of higher than 8-Gb/s/user throughput, less than 2-ms latency, and configurable hardware, a Bayesian inference-based all-message-passing baseband-accelerator (BayesBB) is presented in this article. Benefiting from the pipelined and fully unfolded all-message-passing architecture, BayesBB delivers three unexplored merits: high throughput (9.6-Gb/s), low latency (1.61-ms), and good configurability. Specifically, a ten-gigabit ethernet (XGE) interface with 10.3125-Gb/s SerDes is used, resulting in 9.6-Gb/s throughput. A fully unfolded MIMO-BP detector achieves a detection latency of 1.44-ms, contributing to chip latency of 1.61-ms. A configurable architecture is designed, supporting various B5G/6G applications, for example, the decoding of both 3GPP low-density parity-check (LDPC) codes and polar codes. As a system-level implementation, tests have verified that 16 arrays of BayesBB can handle the BB processing of a $128 \times 128$ CF-mMIMO system with commercial setups, delivering 9.6-Gb/s throughput and >100-b/s/Hz spectrum efficiency (SE).