A Compact Low-Power 16 b SAR ADC Using Reservoir-Charge-Redistributed DAC and Configurable FIA-Based Comparator

This article presents a reservoir-charge-redistributed (RCR) successive approximation register (SAR) analog-to-digital converter (ADC) that facilitates a high linearity and compact area in low power. Conventional on-chip passive charge sharing (PCS) mitigates the bondwire influence on the off-chip reference voltage for the capacitive digital-to-analog converter (DAC) ( $C_{\text {DAC}}$ ). It, however, suffers from a considerable reservoir capacitor ( $C_{\text {REF}}$ ), poor linearity, and dynamic range (DR) loss. Unlike prior PCS schemes, the proposed RCR offers an individual $C_{\text {REF}}$ to each bit trial, and each $C_{\text {REF}}$ only performs charge redistribution once, which is enabled by the subranging architecture. These unique characteristics significantly decouple the compromise between linearity and DR loss and area. Furthermore, a configurable sequentially charged floating inverter amplifier (SC-FIA)-based comparator is also presented to improve energy efficiency further. Incorporated these techniques in a 16-bit SAR ADC, the prototype in 65-nm CMOS process achieves an 80.9-dB signal-to-noise-and-distortion ratio (SNDR) and 100.3-dB spurious-free dynamic range (SFDR) at Nyquist input, consuming $291.7~\mu $ W power from a single supply at 1 MS/s, and yielding a 32.1-fJ/conv.-step Walden figure of merit (FoM_W) and 173.3-dB Schreier FoM (FoM_S).