Asynchronous Architecture Design and Implementation of Physical Memory Protection for RISC-V

Trusted Execution Environment(TEE) delineates se- cure zones within the system, ensuring the security of the execution environment and data confidentiality. However, due to the relatively late start of the RISC-V instruction set ar- chitecture, there are currently few designs for RISC-V-based TEEs, which face challenges such as performance bottlenecks, insufficient support for privilege modes, and the lack of a unified model. Moreover, synchronous circuits’ reliance on extensive clock networks increases area and power usage. This paper introduces an asynchronous Physical Memory Protection(PMP) design for RISC-V, addressing these issues. This scheme provides key hardware support for implementing TEE for RISC-V. The architecture supports user, supervisor, and machine modes, offering 4 B to 16 GB granular protection and up to 64 PMP entries. The initial address and the number of PMP entries can be configured according to requirements, offering high flexibility. After testing, the overall and sub-module functions are correct and align with expectations. Finally, in the 110-nm process, the area of this architecture is 0.47 mm² and the power consumption is only 3.6829 mW.