Mitigation of Vertical Fixed Pattern Noise in CMOS Image Sensors through Analog Offset Dithering and Dynamic Clock Adjustment

Vertical Fixed Pattern Noise (VFPN) is a significant issue in CMOS image sensors that employ column-parallel Analog-to-Digital Converters (ADCs). Variations in column response due to Process, Voltage, Temperature (PVT) characteristics and differential non-linearity (DNL) in ADCs contribute to VFPN, which impacts the perceptibility of noise in images. This paper proposes two primary methods for reducing VFPN: analog offset dithering to mitigate quantization noise and dynamic counter clock adjustment to compensate for DNL variation. Simulation results using sensor measurement data demonstrate that these techniques significantly reduce VFPN by randomizing quantization noise and averaging DNL-induced variations across columns. The proposed methods achieve an improvement in VFPN uniformity of over 70%, effectively enhancing image quality.