A 23.5 TOPS/W Depthwise Separable Convolution Accelerator for Event-based Depth Estimation

Recent efforts to improve energy efficiency in computer vision (CV) tasks, such as depth estimation, focus on integrating event-based cameras with lightweight networks using Depthwise Separable (DWS) Convolutions. Despite remarkable accuracies and hardware-friendly binary signals, existing accelerators have not fully leveraged this combination. This paper proposes a Separated Engine (SE) architecture for binary input feature maps (ifmaps) with dedicated arrays for each DWS stage, eliminating data storage between stages and enhancing array utilization. Additionally, an integrative dataflow incorporating Row, Weight, and Input Stationary (RS, WS, and IS) advantages is introduced to maximize data reuse, supported by an optimized mapping strategy that efficiently loads and updates ifmaps onto the first array. Our gate-level simulation results using 28nm CMOS technology demonstrated a 1.7x improvement in energy efficiency, achieving 23.5 TOPS/W, along with a 13x enhancement in area efficiency, reaching 1785.5 GOP/mm².