Live Demonstration: Smart Watchdog Mechanism for Real-time Fault Detection in RISC-V

This live demonstration relates to our paper titled "Smart Watchdog Mechanism for Fault Detection in RISC-V" also published at ISCAS 2025. Spiking neural networks (SNNs) can realise low power and area implementations compared to traditional neural network models. We present an interactive demonstration of a SNN-based smart watchdog circuit capable of real-time monitoring and detection of errors during program execution in a modern RISC-V processor. The smart watchdogs performance is demonstrated by monitoring the RISC-V core running a control task resembling a safety-critical application, where demo-attendees can inject faults into the program counter register and witness the detection of errors and how control flow errors impacts the motor operation. The demo permits various fault injection patterns, i.e. bit flips and stuck at zero/one faults.