A Lightweight Peripheral Design for RRAM-based LUTs

Resistive random-access memory (RRAM) has garnered increasing interest due to its compact structure size, low energy requirements, and non-volatility. Recently, RRAM crossbars have shown potential for implementing lookup tables (LUTs) for reconfigurable logic. However, due to its analog properties, RRAM suffers from extensive peripherals, such as analog-to-digital converters (ADCs). In this paper, we tackle this problem by combining signal amplification, logic disjunction, and conversion to the digital domain in a single compact gate. As a result, the proposed RRAM-based LUT (R-LUT) design reduces the area per LUT by a factor of four and the peripheral overhead by more than six times. It is also almost three times smaller than an SRAM-based LUT implemented in the same technology. At the same time, it achieves a competitive access frequency of more than 3 GHz while consuming less than 240 fJ per inference, improving all major aspects of state-of-the-art R-LUT designs.