GNN4HHR: A GNN Based Model for Hybrid Hardware Representation

Advancements in technology have led to a continuous reduction in the size of transistors and an increase in the complexity of circuits, posing significant challenges for Electronic Design Automation (EDA) tools. Concurrently, the rapid growth of deep learning has extended its reach across various domains, yielding promising outcomes. Particularly with large-scale datasets, deep learning techniques often demonstrate superior efficiency. Circuits exhibit diverse graph structures spanning from Register-Transfer Level (RTL) to gate-level netlist representations, including Data Flow Graph (DFG), And-Inverter Graph (AIG), and mapped netlist graph, which align well with graph neural networks. Leveraging various open-source tools, GNN4HHR amalgamates disparate graphs from multiple stages into a hybrid hardware representation. The GNN model can effectively distinguish and encode circuits at various stages.