A 83.7% Resource Reduced FPGA-based Wired-Logic DNN Processor by Using Mixed-Precision Module Embedding Into Non-Linear Function LUT

Wired-logic processor architecture is a promising technology for energy-efficient FPGA-based DNN processors by eliminating power-intensive DRAM/BRAM accesses. A key challenge of wired-logic architectures is the substantial hardware resource requirement to implement all neurons and synapses on a single FPGA. While our proposed non-linear neural network (NNN) mitigates this issue by leveraging its high sparsity and binarized weights, the long bit-width of activation values remains a bottleneck, leading to considerable resource consumption and limiting the scalability of DNN models. In this paper, two techniques are proposed to address this challenge: (1) a mixed-precision activation quantization and dequantization module embedded within non-linear function look-up table (NLF-LUT), and (2) input bit-width compression for the NLF-LUT using a clip module and non-uniform step approximation (NSA). These optimizations achieve an 83.7% reduction in hardware resource usage without incurring additional computational overhead or accuracy degradation.