HRC-CIM: Hybrid RRAM-Capacitor Cell based Compute-in-Memory with High Linearity, Parallelism and Energy Efficiency

RRAM-based Compute-in-memory (CIM) has emerged as a promising computing paradigm for artificial intelligence (AI) algorithms. However, the low on/off ratio and high on-current have been the major challenges to enhance the accuracy, parallelism, and energy efficiency. In this paper, we propose a novel Hybrid RRAM-Capacitor (HRC) cell based CIM macro to address these issues. The proposed HRC cell achieves a high on-off ratio with sub-100nA on-current and eliminates direct current path during computation, which significantly enhances both parallelism and energy efficiency. The write-verify scheme for RRAM programming is optimized for HRC cell array, and is further supported by a quantization result calibration technique using a dummy column to ensure high linearity and accuracy in analog domain multiply-and-accumulate (MAC) operations. A HRC-CIM macro has been designed and demonstrated using 28nm technology node, enabling block-level parallelism across 64 rows with 4-bit input per row, and delivering an energy efficiency of up to 40.40 TOPS/W @8b-IN/8b-W.