An All-Digital Voltage Droop Detector Utilizing a Multi-Phase Clock assisted Nyquist Counter

The on-chip droop in processor may cause a severe voltage reduction resulting in a need for on-chip voltage droop detectors. Basically, the digital droop detector indirectly senses voltage changes by reading out the delay information affected by the voltage through a time-to-digital converter (TDC). Conventional all-digital droop detector based on the ring oscillator TDC suffers from high power and area overhead. In order to reduce power consumption and area overhead without introducing the problem of metastability, two techniques are proposed. One is the multi-phase clock sampling technique to achieve the ring stage number compression, therefor the number of sampling register is diminished. The other one is the coarse-fine sharing Nyquist counter for anti-metastability, thus reducing the number of counter. Even with the introduction of the additional all-digital multi-phase clock generator, this design can still achieve an advantage in power and area consumption. Designed at 22nm process, hspice simulations show that the power consumption is reduced by 16.4% and the area is reduced by 12.4% as compared to the SOTA.