AO-EDC: An Accuracy-Oriented Error Detection and Correction Scheme for DVFS System Based on Propagation Detection at Half-Path Points

Error detection and correction (EDC) techniques are conventionally employed in dynamic voltage and frequency scaling (DVFS) systems to eliminate timing margins preserved in ICs. However, existing error detection methods generate warning signals even when no violations occur, resulting in frequent corrections that degrade system throughput. This issue of inaccurate detection worsens with further scaling. To solve this issue, this paper presents an accuracy-oriented EDC scheme, AO-EDC. An accurate detection method, consisting of a propagation detector (PD) and an improved half-path-point insertion method, is proposed. PDs that filter out signals from other paths are inserted at the half-path points of selected paths, reducing inaccurate detection by up to 77.5%. In addition, a half-cycle clock gating circuit is proposed to reduce the redundancy of corrections. Implemented on a 22-nm process FIR circuit, post-layout simulation results demonstrate a 42.4% - 50.0% power reduction and a 106.7% - 1089.9% frequency gain at 0.9 - 0.55 V. The proposed scheme triggers fewer corrections and reduces correction timing waste, addressing the throughput degradation issue during over-scaling in DVFS systems.