Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs

Modern commercial Multi-Processor Systems-Onchips (MPSoCs), targeted for smartphones as well as embedded Artificial Intelligence (AI) and Internet-Of-Things (IoT) applications, require camera interfaces that support the CSI-2 standard and are reconfigurable to support various image data types and throughput requirements. However, existing State-Of-the-Art (SoA) implementations of reconfigurable camera interfaces are proprietary and closed-source.This work proposes, to the best of our knowledge, the first open-source implementation of a reconfigurable image acquisition and processing platform for MPSoC integration. The proposed design is implemented and verified on both FPGA (Zynq ZCU104 FPGA) and ASIC (TSMC 22nm) platforms. The hardware implementation results depict that the proposed design can support a throughput of 9.6 Gbps for streaming 4K resolution images.