A Systematic Comparison of D-Band Power Amplifiers Using MOM- and MOS-Neutralization Capacitors in 22nm FDSOI CMOS

This paper presents a systematic comparison of two high-efficiency and high-gain D-band power amplifiers (PAs) realized in a 22 nm FDSOI CMOS technology. To enhance gain and differential-mode stability, both amplifiers are capacitively neutralized. The two PA test chips are realized each using a different physical implementation of the neutralization capacitance: a) MOM and b) MOS. Using these chips we analyze systematically in measurement the effects of different capacitor types on the circuit performance. We present PA measurements operating up to temperatures of 125 °C and under voltage variations. The PAs feature a high gain of 13 dB and 13.9 dB, while achieving a maximum saturated output power of 7.3 dBm and 6.6 dBm, respectively. Despite the high gain, the PAs offer a 3-dB bandwidth of at least 32 GHz and 27 GHz. Due to their low DC power consumption of only around 29 mW at an operating voltage of 0.8 V, the maximum power-added-efficiency (PAEmax) reaches high values of 12.2 % and 10.2 %, respectively.