An Efficient Number Theoretic Transform Implementation for FIPS-203 on FPGA

The Number Theoretic Transform (NTT) is a key component in modern Post-Quantum Cryptography (PQC) systems, known for its efficient polynomial multiplication capabilities. This paper presents an innovative conflict-free NTT memory architecture that features a mathematically optimized Barrett-based modular reduction with bit correction, tailored for FIPS-203. The primary goal is to significantly reduce hardware resource usage while maintaining high performance and superior efficiency (frequency of operation/area) compared to prior work. Our NTT design, implemented on a Xilinx FPGA Virtex-7, achieves a clock speed of 300 MHz, to the best of our knowledge, the highest reported in the field, outperforming the best-known implementation by 15%. Additionally, it utilizes a single RAMB, one DSP block, 374 LUTs, and 270 registers, making it the most resource-efficient design in the literature, with less than half the hardware usage of prior work. Compared to the leading designs, the proposed architecture reduces LUT utilization by 38%, register usage by 58%, DSP utilization by 50%, and RAMB usage by 75%. As a result, the overall efficiency measured by the area-time product (ATP) surpasses the best design in the literature by a factor of 1.38. These results establish our approach as an optimal solution for applications that require minimal resources and low power consumption without compromising performance.