A Multiplier-Balanced and Area-Efficient Architecture for Low-Frequency Non-Separable Secondary Transform

The existing hardware architectures for Low-Frequency Non-Separable Secondary Transform (LFNST) in VVC suffer from significant resource consumption of multipliers, along with relatively low utilization of these multipliers. In this context, this paper proposes a core unit with balanced multiplier utilization and an area-efficient overall architecture for LFNST. The proposed core unit is based on analyzing the average number of effective multiplications per sample across all transform units, ensuring balanced multiplier utilization and avoiding ineffective multiplications. Additionally, general multipliers can be replaced with a fused circuit that consists only of adders, shifters, and multiplexers. Through the proposed coefficient approximation scheme (CAS), the number of adders in the fused circuit is limited to one, significantly reducing resource consumption. The synthesis results indicate that the proposed design achieves a 72% reduction in normalized area compared to the state-of-the-art work. Furthermore, the proposed CAS can reduce the area of multiplier core unit by 22%, with negligible Bjøntegaard Delta-Rate loss. The proposed architecture supports processing 7680×4320@64fps videos when working at 200 MHz.