Design Technology Co-Optimization for CFET SRAM Cells Considering Double-Sided Signal/Power Routing

High energy efficiency and high-capacity embedded SRAMs are essential for data-centric applications. CFET technology offers a scalable solution to reduce the SRAM cell area. However, the optimal routing of signal and power wires in CFET SRAM to achieve better performance remains unresolved. This study proposes a Design Technology Co-Optimization (DTCO) framework for CFET SRAM cells. After generating 3D cell structures through layouts, parasitic resistance, and capacitance are analyzed for 6T and 8T SRAM arrays. Compared to CFET SRAM using single-sided signal routing with backside power delivery network (BS-PDN), CFET SRAM with double-sided signal/power routing, which efficiently leverages the space above and below the CFET SRAM cells, exhibits reduced parasitic capacitance. This reduction significantly improves read delay, write delay, read power, and write power for both 6T and 8T SRAMs, making it a promising option for high-throughput data-centric applications.