Analysis and Design of Bias-Current-Free Hybrid Phase-Locked Loops with Multi-Phase Time-Interleaved Phase Detector

This paper describes a bias-current-free hybrid phase-locked loop (PLL) architecture that employs a multi-phase time-interleaved phase detector (TI-PD) in a proportional-gain path. To achieve a low reference spur, the reduction of a common-mode (CM) ripple is done through phasor addition by distributing clock edges to multiple paths with a fixed delay. In addition to the spur suppression, the multi-phase TI-PD mitigates the mismatch problem of the multiple paths with an averaging effect. Compared with the single TI-PD-based PLL, the proposed PLL with the multi-phase TI-PD improves the spur performance by 30dB, achieving a reference spur of -81dBc in the simulation. With the fully voltage-domain operation, the proposed PLL is highly promising for low-voltage clock generation systems.