PMOS vs NMOS ZTC References: A Process Technology-Dependent Analysis Framework

This paper presents a detailed theoretical analysis and performance comparison of temperature characteristics and power supply rejection ratio (PSRR) of PMOS and NMOS ZTC operating point based voltage reference circuits. The constraints on MOSFET parameters, such as, a, βμ, βf, & β, to achieve a second order temperature compensation, and the design constraints on IZTC to achieve high PSRR are discussed in detail.The PMOS and NMOS ZTC core voltage reference circuits are designed and simulated in a UMC 65-nm CMOS process, and each occupies an on-chip area of 0.01 mm². The PMOS core reference circuit provides a Vref of 620 mV at a Quiescent current (IQ) of 566 nA from a 1.8 V supply voltage. The PMOS ZTC core reference circuit achieves a temperature coefficient of 10.75 ppm/°C across an operating temperature range of -40° C to 125°C, and a PSRR of -57.3 dB at 1 kHz.