Design Of Majority Carry Save Adder Using Approximation Method For Error-Tolerant Computation

The design and computation of energy efficient approximate adder play a crucial role in VLSI. With recent research focusing on approximate computation in digital circuits, there is a growing method to analyze and optimize the performance of conventional adders. In today's electronics circuits, various delays are considered during verification, making it essential to incorporate area, power, and delay analysis into the design process. The proposed approximation computation aims to reduce errors by employing error-tolerant/resistant techniques. By extending the power and performance tradeoffs of traditional adder designs through error tolerant computation methods, this approach allows for improved circuit design and accurate delay analysis using logical and parasitic delay calculations etc. The proposed system compared with various adders and this paper proposed approximate full adder analyzed using different levels of modified full adders as well the proposed approximate adder and analyzed with various parameter such as area, power and delay using Verilog HDL and Xilinx vivado ISE simulator. The overall efficiency of proposed adder has produced better computational metrics compared to existing conventional adder and the proposed adder design is implemented using cadence virtuoso.