An Efficient Pipeline Programming Scheme Based on 40nm PCM Compute-in-Memory Chip for CNNs

Phase change memory has emerged as a promising candidate for in-memory computing. The conventional write-verify programming scheme for multilevel cells necessitates numerous iterative programming cycles and is susceptible to conductance drift effects. This paper presents the adaptive pulse width programming and pipeline programming scheme to reduce programming cycles by 71.2 % and mitigate the conductance drift. Furthermore, we validate the proposed method through image classification tasks, achieving an accuracy of 91.7% on a PCM-based compute-in-memory chip.