High Density 3D Integration of 2D Transistors via Van Der Waals Lamination

In this work, we review two approaches for realizing high density three-dimensional (3D) integration using twodimensional (2D) transistors via van der Waals (vdW) limitation, including low temperature tier-by-tier lamination, as well as integrating the planar devices onto the silicon sidewall. The two approaches provide alternatives routes for realizing high density vertical 2D transistors as well as 3D integrated system.