FPGA Based AI Inference Accelerator for Low-End Embedded Systems

Aim: This research aims to develop a hardware accelerator to inference AI models for low-end embedded platforms using FPGAs as they are reconfigurable, have parallel and real-time processing capabilities and most importantly they consume very low power makes it best suited for low-end power constrained embedded platforms. In this paper we have implemented Handwritten Digit Classification based on MNIST dataset. Materials and Methods: In this research there are two groups. Group 1 refers to implementation in Raspberry Pi 4B and the power consumption, inference time and accuracy is compared with FPGA implementation. Group 2 refers to FPGA implementation of CNN based handwritten digit classification, where development is done using Xilinx ISE Design Suite and Vivado-HLS software and other softwares for training and quantizing the model. Result: The analysis of the performance comparison between raspberry pi and FPGA based implementation of the same model shows that FPGA based implementation is 14x times faster and 1.8x times power efficient than raspberry pi with negligible effect on accuracy. The FPGA took only 12.9% of total LUTs. Significance less than 0.001 Conclusion: The FPGA based neural network accelerator shows promising results in power efficiency and inference time makes it applicable for use with low-end embedded platforms and makes AI inference possible for them in real-time.