Enhancing 3D DRAM Double-Gate Device Performance by Leveraging the Floating Body Effect

Three-dimensional stackable dynamic random access memory (3D DRAM), featuring horizontally stacked transistors with capacitors, is highlighted as a promising approach to continue DRAM scaling beyond planar architecture. However, the floating body effect (FBE) of this structure is not well understood. Its potential to enhance device performance represents a new direction for the future development of 3D DRAM. This study systematically investigates the physical mechanisms of the FBE and the effect of process parameters on the electrical characteristics of the access transistor. The results show that channel length and doping are not sensitive to leakage current, suggesting that the FBE can be leveraged to reduce the cell area, thereby providing design guidelines for high-density 3D DRAM applications. Furthermore, a novel structure is proposed that perfectly validates the theoretical feasibility.