Multi-level SLC Cache Architecture for SLC-TLC Hybrid Storage

While high-density NAND flash memory, such as triple-level-cell (TLC) memory achieves enhanced storage capacity and cost efficiency by storing three bits per cell compared to the single-level-cell (SLC) flash memory, it exhibits compromised I/O throughput and reduced endurance. To mitigate the intrinsic limitations of TLC flash memory, contemporary designs employ hybrid architectures that reconfigure designated TLC chips to operate in the SLC mode, forming an efficient cache to address latency and endurance constraints inherent to conventional TLC implementations. However, it is challenging to optimize the SLC cache, such as the granularity of cached data and cold/hot data separation. In this paper, we propose supporting a two-level hierarchy (i.e. L1 and L2) of SLC cache stores based on the varying granularity of cached, and we present a mathematical model to direct the segmentation of the L1 and the L2 cache in the SLC region, by considering the garbage collection counts in both level caches, and the write size characteristics of user applications. Besides, we introduce a scheme to select the garbage collection (GC) victim block for retaining the hot data pages in the SLC cache and then improving I/O responsiveness. The evaluation results show that our proposal can improve I/O performance by between 5.4% and 63.3%, in contrast to existing cache management schemes for SLC-TLC hybrid storage.