Thermal-Mechanical Modeling of Package Reflow for Cooling of Future CPU and GPU Devices

Future data centers will employ large-area (greater than 25 mm × 25 mm), high-heat-flux (greater than 1 kW/cm2) central processing unit (CPU) and graphics processing unit (GPU) devices. Such devices, or chips, will necessitate aggressive cooling solutions, including two-phase cooling. In this work, we explore the potential of indium solder as a thermal interface material (TIM) for directly bonding cold plates to chips, providing a low-thermal-resistance pathway. By eliminating the need for multiple TIM layers, this approach enhances thermal efficiency while mitigating stresses by minimizing the coefficient of thermal expansion (CTE) and stiffness mismatch within the device stack-up. We performed thermal-mechanical modeling of the device stack-up to analyze the temperature and stress maps. Our numerical results indicate that the highly viscoplastic and compliant nature of the indium solder TIM prevents excessive thermally induced built-in stress in the device after cooling post-reflow. Furthermore, the numerical results clarify that the thickness of an additional copper-tungsten (C$u$W) layer, as a CTE alleviating component between the cold plate and device, can be minimized as its role is minor in preventing thermally induced stress, and in fact this layer increases package conductive thermal resistance. Thus, optimal thermal-mechanical performance for such large-area devices might be achieved through a minimal indium solder TIM thickness without such intermediary stress mitigation layers.