Signal and Power Integrity Optimization Using Novel Bridge Die and Copper Post Interconnect Design in 2.xD Packaging for Wide I/O Applications

To achieve terabyte/s (TB/s) bandwidth and wide input/output (I/O) essential for processing massive amounts of data, advanced packaging methods have emerged as a promising alternative to traditional semiconductor chip scaling, which is nearing its limits as predicted by Moore's Law. However, as operating frequencies increase, high density routing has become a necessity in wide I/O signaling, leading to signal loss and voltage fluctuations that degrade both signal integrity (SI) and power integrity (PI). To overcome these challenges, this work proposes the use of bridge dies (B/D) and copper posts as an alternative solution. We first examine the SI characteristics at the neural processing unit (NPU) physical layer (PHY) interface and investigate PI properties at the NPU core region to analyze and compare the effects of our proposed design with a conventional silicon interposer. The results show that our design can achieve 6.4 Gbps/lane data transmission in the staggered configuration with a lower loss, lower crosstalk, and an eye width of 0.77 UI, indicating better SI performance. Secondly, PDN impedance and warpage behavior of the advanced packages is also analyzed.