Hybrid Voltage Regulators for High Performance Computing: Analytical Models and Design Methodology

Efficient 48V-to-1V voltage regulators (VRs) embedded near points-of-load (POLs) have the potential to revolutionize PCB-to-POL power delivery in high performance computing (HPC) systems. Hybrid VRs (HVRs) with flying switched capacitors and inductors have been demonstrated as a promising alternative for traditional buck converters (which cannot operate at very fast frequencies near POLs) and switched capacitor (SC) converters (which exhibit high power loss due to hard switching). Despite several successfully fabricated HVRs, the lack of analytical models and application-specific design methodologies has led to an ad hoc, simulation-driven design process and typically suboptimal performance. To address this challenge, generalized analytical models for continuous conduction mode (CCM) HVRs are proposed in this paper. The analytical models are validated using existing HVR architectures in Cadence Virtuoso, achieving an average accuracy of 94.35%. A model-driven design methodology and an efficient design space exploration approach are proposed. To demonstrate the effectiveness of the proposed framework, state-of-the-art (SOTA) HVRs are redesigned using the proposed methodology, leading to adjustments in power switch size and switching frequency. The redesigned HVRs achieve a significant reduction in overall power loss, showcasing the effectiveness of the proposed framework.