SoW-X: A Novel System-on-Wafer Technology for Next Generation AI Server Application

A novel wafer-level 3DIC structure named SoW-X (System-On-Wafer, eXtreme) is proposed to enable integration of up to 16 full-reticle sized ASICs, 80 HBM4 modules and 2.8K 224Gb/s long ranged Serializer/Deserializer (SerDes) channels, delivering up to 260 TB/s for die-to-die and 80 TB/s external bandwidth in total. Compared to a networked compute cluster with the same number of ASICs, SoW-X consumes 17% less power and delivers 46% better performance, resulting in 1.76X better power efficiency. Achieving the performance benchmarks necessitate a reconstructed wafer, which incorporates wafer-wide redistribution layers (RDLs) in conjunction with local-silicon interconnects (LSI), and the integration of several chip-on-wafer (CoW) processes, including ASIC, High Bandwidth Memory (HBM), and IO dies. The crossing wafer RDLs are composed of multiple thick and thin layers to meet electrical requirement of ASIC-to-ASIC and ASIC-to-Connector high speed communications. The connection structures are defined through system technology co-optimization (STCO) analysis to meet the figure of merits of performances. In addition, simulation also shows manageable thermal conditions by liquid cooling.