Process Development and Reliability Investigation of 120 mm × 120 mm Large 2.5D Package with Low Melting Temperature Solder

Advanced packages for high-end applications require higher bandwidth and larger number of I/O signal processing. To achieve the highly demanded performance, heterogeneous integration has been proposed as a technology to integrate different functional chips into a single package system, while the Moore's law is approaching its limit. For example, logic devices integrated with high bandwidth memories in fine pitch have been already commercialized. In order to integrate sophisticated multiple chip, the size of Si interposer and substrate are getting larger. However, an increase in the package size causes various challenges such as warpage control of the package and maintaining package level reliability. We have previously reported the assembly process and reliability of the large size ($120 ~\text{mm} \times 120 ~\text{mm}$) 2.5D package test vehicle [1]. However, a mounting failure occurred on one of the two boards due to significant warpage. In this work, low melting temperature solder (LTS) was adopted between the substrate and the printed circuit board (PCB) to reduce the warpage in solder melting point. In this study, four types joints were examined: LTS and LTS paste (LTS / LTS), LTS and SAC paste (LTS / SAC), SAC and LTS paste (SAC / LTS), SAC / SAC paste (SAC / SAC). LTS / LTS and LTS /SAC have the lowest top reflow temperature. SAC / LTS was in the temperature range between SAC / SAC and LTS / LTS. The warpage of the substrate was less than $200 \mu ~\mathrm{m}$ when subjected to a temperature range between $160{ }^{\circ} \mathrm{C}$ and 200 ${ }^{\circ} \mathrm{C}$, which was sufficient to reduce warpage for mounting. We also conducted thermal cycling test (TCT) to verify whether LTS could withstand fatigue fracture testing.