Microbump Interconnections Using Vertical Wire Technology for the Power Connections Between SoC and Substrate in the Bridge Die-Based Packaging Platform

In this study, vertical wire technology was employed to provide a power-line connection between a system-on-chip (SoC) and a substrate. Metallurgical bonding was performed between the vertical wires and the microbump of the SoC die after wire-ball bonding on the substrate. Palladiumcoated copper (PCC) wires and Au wires were used, and the bonding characteristics and electrical properties of the wires were examined. The soldering joint with the PCC wire was sufficiently robust to withstand the package structure, compared with the Au wire. By combining this technology, flexibility in the design of vertical interconnections can be achieved. The simulation of power integrity (PI) revealed satisfaction within the SoC specifications, even for the longest vertical wire in our condition. Electrical tests showed a much higher failure rate for the Au wire than for the PCC wire. This was due to the excessive Au-Sn intermetallics formed on the solder joint in the Au wire, whereas the PCC wire showed stable growth of the interfacial Sn-Cu intermetallics. This is the first study on a vertical wire applied to a power-connection design, and shows the potential in providing the 2.xD packaging solution from both performance and cost perspectives.