Digital Design of Inter-Die Gap Fill Dielectric Film Processing for C2W Hybrid Bonding Using Finite Element Modelling

The requirement of 3D IC packages with very fine pitch interconnections are driven by the rapid advancement of High-Performance Computing, Artificial Intelligence, Internet of Things, and Electric Vehicle Controls, etc. Chip-to-Wafer Hybrid Bonding (C2W-HB) is the technology that enables Heterogeneous Integration (HI) of dissimilar chips (or chiplets) with such fine pitch interconnections. Current technology of multi-level 3D stacking of dies before encapsulation into a molded die package pose several challenges. High wafer and package warpage, bulky packages due to thicker die-stacks are some of them. Inter-Die Gap Filling (IDGF) process flow is currently being developed address some of these challenges. This process allows deposition of a thick dielectric in the inter-die gap and subsequent thinning of the dies to a much smaller thickness ($<20 \text{um}$). In this work we developed a parametric finite element model to perform digital design of experiments (DDoE) of wafer warpage. In this work we report simulations with a 2-Stack C2W-HB wafer model. Using this the effect of inter-die gap, IDGF thickness, film residual stress, and IDGF material are evaluated to guide the process team. The DDoE results show that the IDGF film thickness and residual stress are the most important parameters to manipulate the wafer warpage. In our on-going work this model is extended to multistack C2W-HB wafer warpage simulations.