Innovative SoIC® Cool-Stacking Technology to Overcome the Thermal Wall of Future High Performance Compute

TSMC SoIC^® has been proven as an enabling technology for high performance system integration. The compact bonding architecture signifies its superiority in heat dissipation, apart from higher bandwidth and more energy-efficient inter-die communication, over other die stacking technologies, such as microbump interconnect. Integrated by the next-generation SoIC^® Cooling Stacking (SoIC^®-CS) technology, a 3D IC consisting of a high-performance compute base die and multilayered high-capacity memory top dies is proven feasible for the first time in this study. SoIC^®-CS is architected to advance the thermal supremacy to surmount the aggravated thermal wall in future AI/HPC applications. A process compatible thin film with a high thermal conductivity (C-layer) is introduced to replace conventional thermally unfavorable dielectric layers in the bonding structure. Compared to other Face-to-Back die stacking technologies, SoIC^® CS exhibits 77% lower thermal resistance than micro-bump scheme, and 37% lower than SoIC^®, as predicted and confirmed by the validated model. SoIC^®-CS also demonstrates 16% higher energy efficient performance (EEP) than SoIC^®. Much higher power densities (more than $1.2 ~\mathrm{W} / \text{mm}^{2}$) can be supported by adopting SoIC^®-CS in next-generation HBM (8-hi, 12-hi and up to 16-hi DRAM layers on an enhanced logic base die) on CoWoS packages. High integration yield on daisy chains has also been successfully demonstrated. The proposed SoIC^®-CS technology unleashes system integration innovations for future AI/HPC applications adopting multilayer chip stacking configuration, such as DRAM-on-logic.