Patterning of Sub 1 μM CD TSV and Bond Pad for Fine-Pitch 2.5D/3D Hybrid Bonding Applications

Achieving smaller feature sizes at a lower cost remains a critical challenge in the semiconductor industry, driven by the increasing demand for higher integration and enhanced performance. This study investigates the feasibility of achieving submicron feature sizes using stepper lithography, a technique that operates near the resolution limits of conventional tools. To address these limitations, key process parameters were identified, including photoresist selection, thickness optimization, and precise exposure energy tuning based on the properties of the underlying film. Experimental studies were conducted on tetraethyl orthosilicate (TEOS) oxide surfaces to evaluate process effectiveness. Through systematic optimization, feature dimensions were successfully reduced to below 800 nm using a stepper tool with a nominal resolution of $1 \mu ~\mathrm{m}$, demonstrating the potential for extending lithographic capabilities. Following lithography and etch process refinement, through-silicon via (TSV) fabrication was performed, achieving an aspect ratio exceeding 10. These advancements in both lithography and etching significantly enhance the feasibility of back-end-of-line (BEOL) processing while reducing overall costs, making it a viable approach for future advanced packaging applications.