Enabling Chip-To-Wafer Hybrid Bonding Scaling to 1Um Pitch With Optimal Power Delivery Using New Bond Via Architectures

Hybrid bonding enables continuous improvement in die-to-die interconnect density, bandwidth, power efficiency, and latency, which are critical for HPC and AI applications. This paper presents a new bond via architecture (Multi-Level Via or MLVs) for the bonding layer by splitting the bond layer vias into two types of vias, direct vias that land on the power delivery planes to minimize the power delivery losses and multi-level vias that land on the lower metal layers to enable continued hybrid bonding pitch scaling. MLVs are compatible with both traditional Front Side Power Delivery Network (FS-PDN) and Backside PDN (BSPDN) technologies. The power delivery and RF passives benefits of MLVs are discussed. Deep ($>8 \mu \mathrm{m}$) and high aspect ratio ($>10: 1$) MLVs traversing multilayer dielectric stacks are demonstrated and the electrical measurements show the expected performance with tight resistance distribution.