Cryo-CMOS Bias-Voltage Generation and Demultiplexing at mK Temperatures for Large-Scale Arrays of Quantum Devices

The rapidly growing number of qubits in semiconductor quantum computers requires a scalable control interface, including the efficient generation of dc bias voltages for gate electrodes. To avoid unrealistically complex wiring between any room-temperature electronics and the cryogenic qubits, this article presents an integrated cryogenic solution for the bias-voltage generation and distribution for large-scale semiconductor spin-qubit quantum processors. A dedicated cryogenic CMOS (cryo-CMOS) demultiplexer and a cryo-CMOS dc digital-to-analog converter (DAC) have been developed in a 22-nm fin field-effect transistor process to control a codeveloped 2-D array designed with 648 single-hole transistors. Thanks to the dissipation below $120 \,\mathrm{\mu }\mathrm{W}$, the whole system operates at temperatures below $70 \,\mathrm{m}\mathrm{K}$ in a custom-built electrical/mechanical infrastructure embedded in a standard single-pulse-tube dilution refrigerator. The bias voltages generated by the cryo-CMOS DAC are demultiplexed to sample-and-hold structures, allowing to store 96 unique bias voltages over a $3 \,\mathrm{V}$ range with a voltage drift between $60 \,\mathrm{\mu }\mathrm{V}/ \mathrm{s}$ and $18 \,\mathrm{m}\mathrm{V}/ \mathrm{s}$. This work demonstrates a tight integration at $\,\mathrm{m}\mathrm{K}$ temperatures of cryo-CMOS bias generation and distribution with a dedicated large-scale quantum device. This showcases how this approach simplifies the wiring to the electronics, thus facilitating the scaling up of quantum processors toward the large number of qubits required for a practical quantum computer.