A Triristor With Tri-Stable States Using Double Latches

A tri-stable resistor (triristor), structurally identical to a MOSFET built on a bulk silicon wafer, is demonstrated using double latches arising from single transistor latch (STL). It has two spatially and voltage-separated STL events: the first latch and second latch. Each causes an abrupt transition between current levels, providing a stable state in between. The first latch, occurring at a moderate drain voltage ( ${V}_{\text {D}}$ ), begins with bulk punchthrough current ( ${I}_{\text {bulk,punch}}$ ) flowing through the lightly doped body and triggers the first impact ionization (II). The second latch, triggered at a higher ${V}_{\text {D}}$ , starts with surface subthreshold current ( ${I}_{\text {surf,subth}}$ ) near the Si-SiO2 interface, leading to the second II. These double latches result in tri-stable states, making the triristor applicable to ternary logic, and multi-valued memory as well as other innovative applications.