Discontinuous Pulse-Width Modulation With Balanced DC-Link Capacitor Voltages for Three-Phase Four-Level Inverters

Compared with three-level inverters, four-level inverters need more switching times to balance the dc-link capacitor voltages, lowering the efficiency. This article proposes a four-level discontinuous pulsewidth modulation (4L-DPWM) to reduce the switching loss of inverters by clamping the switching state of one phase, and the dc-link capacitor voltage balancing is achieved as well. First, the subsector division is optimized. In each subsector, the switching-state sequence consists of five basic vectors that clamp the phase with the highest current under the unity power factor condition. Then, voltage balancing equations are derived and considered when calculating the dwelling times of five basic vectors. As a result, the switching loss is reduced, and the dc-link capacitor voltage is balanced. Finally, A 6-kVA three-phase four-level inverter prototype is built to conduct experiments. Experimental results show that the proposed 4L-DPWM scheme can effectively balance the capacitor voltage and achieve higher efficiency.