A Highly Efficient SEU Tolerant Radiation Hardening 14 T SRAM Cell for Aerospace Applications

Modern state-of-the-art VLSI circuits such as SRAMs covers a greater part of the chip area. As technology scales down and moves into the nanometer regime, radiation-induced particles in space induces greater impact in memory devices such as SRAMs. Therefore, this enhances the rate of soft error. In this article, a highly efficient SEU tolerant 14 T radiation-hardened SRAM cell (RHSC-14 T) is presented. This work demonstrates that the RHSC-14 T design in tolerant to both single and dual node upsets and provides good critical charge than most of the considered SRAM designs. The relative strength of the proposed work over QUATRO-10 T, PS10 T, NS10 T, RHD12 T, WE-QUATRO, RSP-14 T, QUCCE10 T, QUCCE12 T, QCCM10 T, QCCM12 T, ILS-14 T RHMD10 T, SEA14 T and SEI-14 T is determined by comparing the read delay, write delay, Static Noise Margin, critical charge, hold power consumption, relative area and probability of radiation occurrence. The simulations are done using UMC 65 nm CMOS technology. The proposed RHSC-14 T SRAM design exhibits 1.279x/ 1.346x/ 1.551x/ 1.184x/ 1.094x/ 1.046x/ 1.108x/ 1.229x 1.189x shorter read delay (TRA) than QUATRO-10 T/ PS10 T/ NS10 T/ RHD12 T/ RSP-14 T/ QUCCE10 T/ QCCM10 T/ RHMD10 T/ SEA14 T @VDD = 1 V. The proposed design has also lower write delay compared to remaining RHBD SRAM designs. Also, the proposed cell consumes lower hold power. However, these gains come at the expense of moderate RSNM. Overall, the performance quality merit of the cell has been evaluated such that it provides good radiation-tolerance capability and overall better performance.