Energy-Efficient Hybrid STT-MTJ/CMOS Circuit for Machine Learning-Assisted Neuromorphic Computing Applications

The CMOS-based neuromorphic computing system (NCS) face significant challenges, such as increasing energy usage and vast area footprints, surpassing the efficiency of biological brains. Spin transfer torque magnetic tunnel junction (STT-MTJ), a type of spin device, offers convenient benefits, including nonvolatility, increased energy efficiency, increased speed of operation, and compatibility with CMOS, making them ideal for energy-efficient spiking NCSs that exhibit neuronal behavior. However, the high energy consumption in spintronic-based NCS, primarily due to the high write current required for MTJ switching, remains a significant challenge as neurons in these systems tend to stay active longer than necessary. To address this challenge, we introduce a novel hybrid STT-MTJ/CMOS write terminate circuit (SM-WTC) that efficiently terminates the MTJ current efficiently after MTJ-state switches, significantly improving energy consumption and speed by $2.6\times $ and $2.3\times $ , compared to conventional NCSs. The proposed SM-WTC technique achieves energy consumption reductions of 52.7%, 58.3%, and 62.18% compared to prior work in real-time sensing (RTS) circuit, common-mode tracking and terminating circuit (CM-TTC), and conventional-NCS, respectively. A Cadence Virtuoso simulation using 65-nm CMOS technology has been used to evaluate the proposed circuit. Furthermore, SM-WTC-based NCS achieves a 67.2% improvement in energy-delay product (EDP) over conventional NCS for image edge detection. These advancements position SM-WTC as a commercially viable solution for next-generation artificial intelligence (AI) accelerators and brain-inspired computing architecture.