Optimizing Power and Area in VLSI Design for Pulse Width Modulation Systems using an Adaptive Method

Aim: This study proposes an efficient VLSI architecture design for pulse width modulation using an adaptive method to improve the performance and energy efficiency of power electronic systems. Materials and Methods: The proposed architecture is implemented using Verilog HDL and verified through simulation and synthesis on FPGA platforms. Group 1 refers to the novel adaptive method using Dynamic Bit-Length Control with 15 iteration samples, while Group 2 refers to a pre-scaled method with 15 iteration samples. The adaptive PWM architecture demonstrated a 20% reduction in overall area and a 30% decrease in power consumption compared to the pre-scaled method. Result: The design demonstrates significant power efficiency, utilizing only 1.065 W of power with 90% dynamic power and minimal resource consumption. The PWM signal achieves precise duty cycle control with reduced latency. Breaking down the dynamic power further, the signals contribute 0.229 Watts (24%), the core logic consumes 0.153 Watts (16%), and IO(input, output) operations account for the largest portion at 0.572 Watts (60%) with a significance of about 0.0406 for area and 0.0385 for power Conclusion: The proposed VLSI architecture for adaptive PWM provides an efficient and versatile solution for applications requiring high-performance pulse width modulation, characterized by a compact area and low power consumption.