A Method for Co-Design of Compiler and Large-Scale HPC System Architecture

The field of High-Performance Computing (HPC) is advancing towards large-scale systems, playing a crucial role in scientific research, engineering, and industrial applications by processing vast datasets and solving complex problems. It is essential to explore the design of large-scale HPC system architectures through simulation and to improve the performance of these designs using compilation techniques. To tackle the challenge of optimizing large-scale High-Performance Computing (HPC) system architectures and compiler designs, we propose a method that integrates Multi-Level Intermediate Representation (MLIR) with the Structural Simulation Toolkit (SST). This approach enables the concurrent design and simulation of large-scale HPC architectures and compilers, facilitating early-stage optimization. We extend an MLIR-based cryptographic algorithm compiler and validate the effectiveness of our method through its integration with SST. The example study demonstrates how this method can provide more comprehensive guidance in selecting the scale of high-performance architectures and task partitioning. This collaborative design process enables researchers and engineers to more efficiently develop HPC systems, advancing both compilation techniques and HPC system architectures.