CNTFET-Based 12T Sram Cell Design With Enhanced Write Margin and Read Performance Using Indep Technique

In nanoscale SRAM design, Various design issues arise, such as cell stability, power dissipation, and delay, particularly in nanoscale SRAM due to the thinning of the technology geometry. There are major scaling problems in cell stability, power dissipation, and delay for chasing downsized dimensions with the use of metal oxide semiconductor field effect transistors (MOSFETs). Recent studies have shown that CNTFETs in combination with the INDEP technique can significantly improve energy efficiency, power dissipation, and delay performance in SRAM cells. Here, we present a new 12T SRAM cell that uses CNTFET technology and the INDEP technique to improve performance metrics and stability during the hold, read, and write phases. The anti-fuse cells of the design also contain independent read and write ports enabling lower leakage and higher SNM for hold, read and write states. Employing the CNTFET Stanford model of dimensions about 32 nm, the results of simulation show that the designed 12T INDEP-CNTFET SRAM cell has better functionality than ordinary designs and can optionally decrease the leakage electricity to as much as four orders lower than MOSFET or 8T static memory. Increased write static noise margin (WSNM) and reduced write access time are also features of the 12T INDEP-CNTFET. The cell also demonstrates a reduction in read access time and increased energy efficiency with improved read access speed among the devices tested.