Discrete-Time State Feedback Design Approach in a Digitally Current Mode Controlled Boost Converter for Improving Transient Performance and Stability

The design tradeoff between the phase margin and the gain crossover frequency ($\omega _{c}$) remains a challenge using an output feedback-based design approach in a current mode controlled (CMC) boost converter, primarily due to the presence of a right-half-plane (RHP) zero in its control-to-output transfer function. A state feedback (SF) design approach is an effective alternative in a digital CMC (DCMC) boost converter. Using discrete-time (DT) models, this article presents a direct SF-based design approach to optimize the converter’s dynamic performance at higher $\omega _{c}$ in the presence of constraints on voltage/current overshoot/undershoot, irrespective of the type of load. The DT closed-loop model is shown to be valid for a higher $\omega _{c}$ and able to accurately predict the fast-scale instability due to the sampling delay under higher controller gains. A boost converter laboratory prototype is made, and the DCMC is implemented using an FPGA device. Superior transient performance using the proposed design approach at higher bandwidths, ${\omega _{c}} \in [ {0.5\,{\omega _{\mathrm{{rhp}}}},\,\,{\omega _{\mathrm{{rhp}}}}} ]$, is demonstrated using simulation and experimental results under constant resistive load, constant current load, and constant power load. The controllability property of the proposed design approach ensures the system’s robustness and insensitivity against parameter variations and input voltage disturbance.