A 64.7 nA, –65dB@1 kHz, and Dual-Output CMOS Voltage Reference With Multi-Loop Active Load Without Trimming

This brief presents a trimming-less and dual-output CMOS voltage reference for low power applications based on specific active load and body bias technology. A multi-loop active load connected in a nested structure is proposed to reduce power supply sensitivity. Without trimming, two reference voltages are obtained in a single branch. The proposed voltage reference is fabricated in standard 180nm CMOS technology. Measurement results show that, the proposed voltage reference achieves excellent performance. The untrimmed average temperature coefficient of $\text {V}_{\text {REF1}}$ and $\text {V}_{\text {REF2}}$ are 28.7ppm/°C and 97.5ppm/°C in the range from –40°C to 125°C. The line sensitivity of $\text {V}_{\text {REF1}}$ and $\text {V}_{\text {REF2}}$ are 0.051%/V and 0.034%/V from 1 to 1.8V supply. High power supply rejection ratio of –65dB at 1kHz is obtained and power consumption is 64.7nW.