A Low-Latency, Highly-Pipelined Hardware Architecture for H.266/VVC Dependent Quantization

In comparison to H.265/HEVC, H.266/VVC introduces a novel quantization tool—dependent quantization, which significantly reduces the rate while maintaining the same video quality. However, due to the quantization process of the transform coefficients being highly dependent on the quantization results of the preceding coefficients, the computational parallelism is low, making it unsuitable for hardware pipeline processing and difficult to achieve real-time encoding. To enhance parallelism, this paper optimizes the rate estimation algorithm based on dependent quantization and designs a multi-quantization state parallel quantization structure, implementing a pipeline-based dependent quantization hardware architecture. The main contributions of this paper are as follows: 1) A hardware-friendly rate estimation algorithm is proposed for calculating the quantization level rate-distortion cost, eliminating the dependency on context templates. 2) A multi state parallel quantization hardware structure is designed to improve the quantization parallelism. Among the multiple generated quantization paths, the shortest quantization path is output by comparing the cumulative rate-distortion cost. Additionally, two trellis memories are introduced during the quantization level output phase, using a ping-pong operation to maximize the output throughput of the quantization module. 3)An 8-stage pipeline computation architecture is proposed for dependent quantization, and the dependent quantization hardware module is implemented, with a computing performance capable of quantizing one transform coefficient per cycle. Experimental results show that the dependent quantization hardware module designed in this paper achieves a maximum frequency of 276MHz, with encoding average speed reaching $3840\times 2160$ @31.4,83.5,164.5,242.8fps under QP = 22,27,32,37 conditions. In both All Intra and Random Access configurations, the Bjontegaard Delta Bitrate (BDBR) only increases by 0.81% and 0.85% compared to the standard reference software VTM18.0, respectively. Compared to existing hardware quantization schemes, our approach offers outstanding quantization efficiency and quantization speed.