Fast IR-Drop Model of Memristor Crossbars and Circuit Compensation Utilizing DTCO

The utilization of compute-in-memory (CIM) based on a memristor crossbar has been identified as a promising computational solution for neural networks. However, the IR-drop effect in the analog CIM caused by wire resistance poses a significant challenge in scaling up crossbar arrays for matrix operations, thereby constraining further improvements in computational efficiency and throughput. This work addresses two principal issues of IR-drop through a proposed solution and analysis of the intrinsic physical equations of the crossbar. First, a rapid IR-drop model was established, which facilitates the investigation of the impact of wire resistance on neural networks. Second, a designtechnology co-optimization method was employed to design peripheral compensation circuits that address the precision degradation caused by IR-drop based on the analysis results from both the model and simulation. The model achieves a high level of accuracy (over 95%) with extremely low computation complexity (O( ${n}\text {)}\text {)}$ and the lowest cache cost. The memristor variations were effectively suppressed, enabling the development of a memristor array-based circuit with an ultralarge scale of 5M cells, which significantly exceeds the largest CIM macro currently available.